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AMD Rolls Out Cost-Optimized FPGA Family

As FPGAs target more applications, AMD’s newest family—launched today—balances cost and power with performance.

Extending its programmable logic portfolio, today AMD has revealed its latest cost-optimized line of Spartan FPGAs. As FPGAs are used in more and more products and devices, ranging from particle colliders to extraterrestrial rovers, designers may often find themselves looking for a programmable logic chip that strikes a careful balance between cost, size, and performance. This market is what AMD hopes to address with its latest chip series: the Spartan UltraScale+ family.

In order to learn more about the new FPGA family, we sat down with Rob Bauer, senior manager of product marketing at AMD to learn more about the features and performance upgrades AMD has included in its newest chip series. We will share those insights here, along with a discussion to highlight the cases that could benefit especially from the newest AMD FPGA.

Multivariate Cost Optimization

The UltraScale+ family of Spartan FPGAs put cost above all else, giving designers a way of including the latest programmable logic chips in their own devices. This is accomplished in a variety of ways that directly and indirectly impact the final cost of the devices.

In terms of direct impacts, AMD leverages modern silicon technology combined with a higher number of I/O ports to reduce costs associated with the Spartan UltraScale+ family. In addition, power and size reductions thanks to the move to a 16 nm process ensure that the chips take up less board space and require less energy to operate, further reducing costs.

Indirectly, AMD sets itself apart from competitors by offering a unified software stack for the development and simulation of Spartan UltraScale+ devices. This aids in development times by reducing the amount of software needed and offers a quick learning curve for designers familiar with other AMD devices.

Bauer explained the utility of a unified software stack. “Whether you’re programming a small Spartan UltraScale+ device or the world’s largest FPGA, the VP1902 that we introduced last year, it’s the same tool across the entire portfolio,” he says.

Increased I/O Availability

A key selling point of the Spartan UltraScale+ series is its applicability to edge devices. This is accomplished with (in addition to the above benefits) high numbers of I/O ports and improved security features compared to previous generations.

In I/Os, the UltraScale+ family offers up to 572 ports with voltage support up to 3.3 V, allowing for the simultaneous control and measurement of many different peripheral devices that could be present at the edge. In addition, hardened DDR4/5 and PCIe Gen4 connectivity blocks are included onboard, reducing the number of logic cells required for communication interfaces.

On the security side, the Spartan UltraScale+ is NIST-approved in Post-Quantum Cryptography, ensuring that edge devices will not be susceptible to malicious attacks if quantum computers become readily available to consumers. 

This is a key feature of the new chip series, especially in the case of edge devices according to Bauer. 

“We have more devices at the edge collecting more data. So user data, privacy of the user, privacy and protection of the intellectual property is increasingly important.”

In addition, the security features of the Spartan UltraScale+ series further reduces development times, adding more utility to the new chip series.

Spartan UltraScale+ chips are expected to be available for sampling and evaluation by Q2 2025, with documentation available now.

Balancing Cost and Performance

As the market for FPGAs continues to expand alongside AMD’s Cost-Optimized FPGA portfolio, designers now have access to a vast array of chips that can be used in their latest designs. And while FPGAs are not a one-size-fits-all solution, AMD is confident that the Spartan UltraScale+ series will be useful to many designers

“Spartan FPGAs are some of the most ubiquitous devices out there, used across pretty much every industry and application,” says Bauer. “And so it’s no surprise that we’re trying to support as wide a range of requirements as we can for design engineers.”

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